The present invention relates to a logic circuit and a semiconductor integrated circuit.
A buffer circuit, which is a logic circuit that outputs a positive logic level, is widely used in a semiconductor integrated circuit and the like today for the purpose of enhancing the driving capability and the like. Generally, the buffer circuit is configured to output an input logic value as it is. Various configuration examples of the buffer circuit have been proposed (Japanese Unexamined Patent Application Publication No. 06-77805, for example).
FIG. 10 is a circuit diagram showing a configuration of a typical buffer circuit 500. As shown in FIG. 10, the buffer circuit 500 includes an input terminal 51, an inverter circuit 52, a first delay difference generator 53, a second delay difference generator 54, a PMOS transistor 55, an NMOS transistor 56, and an output terminal 57. The input end of the inverter circuit 52 is connected to the input terminal 51. The input end of the first delay difference generator 53 is connected to the output end of the inverter circuit 52, and the first delay difference generator 53 causes a difference in delay to occur between the rising edge delay time and the falling edge delay time of an input signal IN. The input end of the second delay difference generator 54 is connected to the output end of the inverter circuit 52, and the second delay difference generator 54 causes a difference in delay, which is different from the difference caused by the first delay difference generator 53, to occur between the rising edge delay time and the falling edge delay time of the input signal IN. The source electrode of the PMOS transistor 55 is connected to a first power supply (an internal power supply voltage VINT), the drain electrode thereof is connected to the output terminal 57, and the gate electrode thereof is connected to the output end of the first delay difference generator 53. The source electrode of the NMOS transistor 56 is connected to a second power supply (a ground voltage GND), the drain electrode thereof is connected to the output terminal 57, and the gate electrode thereof is connected to the output end of the second delay difference generator 54.
FIG. 11 is a timing chart showing an operation of the buffer circuit 500. In the buffer circuit 500, the first delay difference generator 53 causes a delay difference to occur so that the falling edge delay time tPHL1 is greater than the rising edge delay time tPLH1, and the second delay difference generator 54 causes a delay difference to occur so that the falling edge delay time tPHL2 is smaller than the rising edge delay time tPLH2, for example. As a result, the input signal IN that is input to the input terminal 51 is inverted by the inverter circuit 52 into an inverted output signal Va. A delay occurs in the falling edge of a gate voltage Vb by the first delay difference generator 53. On the other hand, a delay occurs in the rising edge of a gate voltage Vc by the second delay difference generator 54.
Because a MOS transistor turns ON when the gate voltage is |VGS−Vth|≧0 (VGS is a gate-source voltage, and Vth is a threshold voltage of a single transistor), a PMOS transistor generally becomes ON when an input is at “L” level, and an NMOS transistor generally becomes ON when an input is at “H” level. It is thereby possible to prevent the PMOS transistor 55 and the NMOS transistor 56 from becoming ON state simultaneously upon switching of the input signal IN by the first and second delay difference generators 53 and 54. Because there is a period when the PMOS transistor 55 and the NMOS transistor 56 are both OFF (periods of tPHL1-tPHL2 and tPLH2-tPLH1 in FIG. 11), an instantaneous through current It decreases. Note that, OUT in FIG. 11 is an output signal that is output to the output terminal 57.
Further, a technique that reduces switching noise by switching the power supply is disclosed as another example of a buffer circuit (Japanese Unexamined Patent Application Publication No. 09-36727).